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Sheet目录3841

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SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

15.3

Functional Description

The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.

The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a

20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.

The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the

Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic

Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, pro-

vided the interrupt is enabled (PITIEN in PIT_MR).

Writing a new PIV value in PIT_MR does not reset/restart the counters.

When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the over-

flow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives

the number of periodic intervals elapsed since the last read of PIT_PIVR.

When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no

effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without

clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.

The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit

only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit

is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts count-

ing, only if the PITEN is set again.

The PIT is stopped when the core enters debug state.

Figure 15-2. Enabling/Disabling PIT with PITEN

MCK Prescaler

PIV

PIV - 1

PITEN

CPIV

restarts MCK Prescaler

APB cycle

read PIT_PIVR

PICNT

PITS (PIT_SR)

MCK

APB Interface

APB cycle

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